Programmable Communication Interface 8251 Block Discription

Programmable Communication Interface 8251

·                     The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous serial data communication.

·                     It supports the serial transmission of data.

·                     It is packed in a 28 pin DIP. 

The functional block diagram of 825 1A consists five sections. They are:

• 1.     Read/Write control logic
• 2.     Transmitter
• 3.     Receiver
• 4.     Data bus buffer
• 5.     Modem control.

The description of each block is as follows :

Read/Write control logic: 

·                     The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register.

·                     It monitors the data flow.

·                     This section has three registers and they are control register, status register and data buffer.

·                     The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers.

·                     When C/D(low) is high, the control register is selected for writing control word or reading status word.

·                     When C/D(low) is low, the data buffer is selected for read/write operation.

·                     When the reset is high, it forces 8251A into the idle mode.

·                     The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

Summary

C/D(low)- high àwriting control word and reading status word

C/D(low)-0àread/write operation

Resetà high àidle mode

Transmitter section: 

·                     The transmitter section accepts parallel data from CPU and converts them into serial data.

·                     The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits.

·                     When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.

·                     If buffer register is empty, then TxRDY is goes to high.

·                     If output register is empty then TxEMPTY goes to high.

·                     The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART.

·                     The clock frequency can be 1,16 or 64 times the baud rate.

Receiver Section: 

·                     The receiver section accepts serial data and convert them into parallel data

·                     The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.

·                     When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again.

·                     If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.

·                     The CPU reads the parallel data from the buffer register.

·                     When the input register loads a parallel data to buffer register, the RxRDY line goes high.

·                     The clock signal RxC (low) controls the rate at which bits are received by the USART.

·                     During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.

·                     During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.

MODEM Control:

·                     The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines.

·                     This unit takes care of handshake signals for MODEM interface.