8259 Block Diagram and Discription

·         8259 Programmable interrupt controller

·         8259A Interrupt Controller is designed to transfer the interrupt with highest priority to the CPU, along with interrupt address information.

8259 Block diagram

·        

READ/WRITE LOGIC


This is a typical read/write control logic. When A0 is low, the controller is selected 
to write a command. The chip select and A0 is used for determining port address.


CONTROL LOGIC


This has 2 pins INT(interrupt) and INTA(bar)(interrupt acknowledge) as input.
The INT is connected to MPU. Whereas the INTA(bar) is interrupt acknowledege 
from MPU.


INTERRUPT REGISTER AND PRIORITY RESOLVER


The interrupt request register(IRR) has 8 input lines. IR0 – IR7 for interrupts.
The request are stored in the register. 
The In service register(ISR) stores all levels that are currently being serviced. 
The interrupt mask register(IMR) stores the masking bits of interrupts lines to
be masked.
The priority resolver(PR) examines these registers and determines whether to send
INT to MPU or not.


CASCADED BUFFER/COMPARATOR


This is used to expand number of interrupts levels by cascading 2 or more 8259’s.

·         features

• Eight interrupt request input per chip
• Up to 64 interrupt request inputs per system
• Edge or level triggered interrupt request inputs
• Individually maskable interrupt requests

• Programmable interrupt request priority orders
• Polling operation capability
• Extended mode with cascade connection of external interrupts
• Supports Slave mode in extended mode