Control unit

A control unit is circuitry that directs operations within the computer's processor by directing the input and output of a computer system. The processor then controls how the rest of the computer operates (giving directions to the other parts and systems). A control unit works by gathering input through a series of commands it receives from instructions in a running programs and then outputs those commands into control signals that the computer and other hardware attached to the computer carry out.

The control unit is basically circuitry inside the CPU, controlling the operations inside the CPU and "directing traffic" in a sense. The functions a control unit performs can depend on the type of CPU, since the varying degre

CU functions are as follows:

• Controls sequential instruction execution
• Interprets instructions
• Guides data flow through different computer areas
• Regulates and controls processor timing
• Sends and receives control signals from other computer devices
• Handles multiple tasks, such as fetching, decoding, execution handling and storing results
  

Discuss and Differentiate Hardware and Micro-programmed control unit?

There are two major types of control organization:  hardwired control and  microprogrammed control. Hardware Control Unit  In the hardwired organization, the control logic is implemented with gates, flip-flops, decoders, and other digital circuits. It has the advantage that it can be optimized to produce a fast mode of operation. In the microprogrammed organization, the control information is stored in a control memory. The control memory is programmed to initiate the required sequence of microoperations. A hardwired control, as the name implies, re­quires changes in the wiring among the various components if the design has to be modified or changed. In the microprogrammed control, any required changes or modifications can be done by updating the microprogram in control memory. Micro Programed Control Unit The control memory is assumed to be a ROM, within which all control information is permanently stored. The control memory address register specifies the address of the microinstruction, and d the control data register holds the microinstruction read from memory. The microinstruction contains a control word that specifies one or more micro-operations for the data processor. Once these operations are executed, the control must determine the next address. The location of the next microinstruc­tion may be the one next in sequence, or it may be located somewhere else in the control memory. For this reason it is necessary to use some bits of the present microinstruction to control the generation of the address of the next microinstruction. The next address may also be a function of external input conditions. While the microoperations are being executed, the next address is computed in the next address generator circuit and then transferred into the control address register to read the next microinstruction. Thus a microinstruc­tion contains bits for initiating microoperations in the data processor part and bits that determine the address sequence for the control memory. The next address generator is sometimes called a microprogram sequencer, as it determines the address sequence that is read from control memory. The address of the next microinstruction can be specified in several ways, depending on the sequencer inputs. Typical functions of a microprogram sequencer are incrementing the control address register by one, loading into the control address register an address from control memory, transferring an external address, or loading an initial address to start the control operations. The control data register holds the present microinstruction while the next address is computed and read from memory. The data register is some-times called a pipeline register. It allows the execution of the microoperations specified by the control word simultaneously with the generation of the next microinstruction. This configuration requires a two-phase clock, with one clock applied to the address register and the other to the data register. The system can operate without the control data register by applying a single-phase clock to the address register. The control word and next-address information are taken directly from the control memory. It must be realized that a ROM operates as a combinational circuit, with the address value as the input and the corresponding word as the output. The content of the specified word in ROM remains in the output wires as long as its address value remains in the address register. No read signal is needed as in a random-access memory. Each clock pulse will execute the microoperations specified by the control word and also transfer a new address to the control address register. In the example that follows we assume a single-phase clock and therefore we do not use a control data register. In this way the address register is the only component in the control system that receives clock pulses. The other two components: the sequencer and the control memory are combinational circuits and do not need a clock.  Advantage The main advantage of the microprogrammed control is the fact that once the hardware configuration is established, there should be no need for further hardware or wiring changes. If we want to establish a different control sequence for the system, all we need to do is specify a different set of microin­structions for control memory. The hardware configuration should not be changed for different operations; the only thing that must be changed is the microprogram residing in control memory.

RISC CISC ,difference,vs,Advantage ,disadvantage

RISC (Reduced Instruction Set Computer)
RISC stands for Reduced Instruction Set Computer. To execute each instruction, if there is separate electronic circuitry in the control unit, which produces all the necessary signals, this approach of the design of the control section of the processor is called RISC design. It is also called hard-wired approach.
Examples of RISC processors:

• IBM RS6000, MC88100
• DEC’s Alpha 21064, 21164 and 21264 processors

Features of RISC Processors:
The standard features of RISC processors are listed below:

• RISC processors use a small and limited number of instructions.
• RISC machines mostly uses hardwired control unit.
• RISC processors consume less power and are having high performance.
•  Each instruction is very simple and consistent.
• RISC processors uses simple addressing modes.
• RISC instruction is of uniform fixed length.

RISC - Advantages

• Simple instructions allows RISC processors to be easier to design and cheaper to produce.
• Requires less transistors there allowing the processors to be smaller.
• Easier to create powerful optimized compilers since there are fewer instructions in the instruction set

RISC - Disadvantages

• RISC architecture puts a greater burden on the software.
• RISC instructions will need a lot more memory to store all of the instructions.. 

CISC (Complex Instruction Set Computer)
CISC stands for Complex Instruction Set Computer. If the control unit contains a number of micro-electronic circuitry to generate a set of control signals and each micro-circuitry is activated by a micro-code, this design approach is called CISC design.
Examples of CISC processors are:

• Intel 386, 486, Pentium, Pentium Pro, Pentium II, Pentium III
• Motorola’s 68000, 68020, 68040, etc.

Features of CISC Processors:
The standard features of CISC processors are listed below:

• CISC chips have a large amount of different and complex instructions.
• CISC machines generally make use of complex addressing modes.
• Different machine programs can be executed on CISC machine.
• CISC machines uses micro-program control unit.
• CISC processors are having limited number of registers.

The advantages of CISC
At the time of their initial development, CISC machines used available technologies to optimize computer performance.

• Microprogramming is as easy as assembly language to implement, and much less expensive than hardwiring a control unit.
• The ease of microcoding new instructions allowed designers to make CISC machines upwardly compatible: a new computer could run the same programs as earlier computers because the new computer would contain a superset of the instructions of the earlier computers.
• As each instruction became more capable, fewer instructions could be used to implement a given task. This made more efficient use of the relatively slow main memory.
• Because microprogram instruction sets can be written to match the constructs of high-level languages, the compiler does not have to be as complicated.

The disadvantages of CISC
Still, designers soon realized that the CISC philosophy had its own problems, including:

• Earlier generations of a processor family generally were contained as a subset in every new version --- so instruction set & chip hardware become more complex with each generation of computers.
• So that as many instructions as possible could be stored in memory with the least possible wasted space, individual instructions could be of almost any length---this means that different instructions will take different amounts of clock time to execute, slowing down the overall performance of the machine.
• Many specialized instructions aren't used frequently enough to justify their existence --- approximately 20% of the available instructions are used in a typical program.
• CISC instructions typically set the condition codes as a side effect of the instruction. Not only does setting the condition codes take time, but programmers have to remember to examine the condition code bits before a subsequent instruction changes them.

RISC                                                                               CISC

1.Emphasis on hardware                                                  1.Emphasis on SOFTware
2.Includes both Single-clock cycle simple                          2.Single-clock cycle reduced instructions only
instruction and multi-clock cycle complex
instructions 
3.Memory to memory:                                                       3.Register to Register:
Load and store are incorporated as part                              Load and Store are independent instructions
of instruction
4.Smaller code size                                                           4.LARGE code size
5.High cycles per second                                                   5.Low cycles per second
6.Transistors used for storing complex                                6.Transistors used for memory register
instruction
7.Easier  to  design    a compiler                                          7.Harder  to  desin    a     Compiler                                  

 

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Reduced Instruction Set Computing (RISC) is a CPU design concept that seeks gains in power as a trade-off for simplified instructions. This design philosophy is directly opposed to Complex Instruction Set Computing (CISC), which is the basis of the x86 style processors of the vast majority of home PCs and laptops.

1. Performance-Oriented

   • The construction of the RISC processor is such that performance is the priority, rather than raw power. When RISC and CISC were developed, the bottleneck of microprocessors was power, meaning that CISC won out and efficient, performance-oriented chips were used less and less. RISC came back into vogue when the need increased for chips that make efficient use of portable battery power.

   Less Versatile

   • Since the instruction set is so simple, that is, one instruction per cycle, RISC processors tend to be better used for simple and repetitive logic operations. CISC processors are truly "general purpose," meaning that they can pipeline multiple instructions at once without a preference for simpler or more complex applications. RISC processors need to be programmed in a very particular fashion.

   Simpler

   • The performance orientation of the RISC architecture is due to its simple and efficient instruction set. This simplicity means that RISC processors are easier to design and inexpensive to produce, making them ideal for purpose-built and cheap computing machines that execute repetitive instructions.

   Long Instruction Strings

   • RISC processors can be adapted to run CISC style instruction strings, but they are incredibly inefficient at doing so. Since a RISC processor can only handle one instruction string at a time, code needs to be more compartmentalized and, therefore, more complicated.